1. Field of the Invention
The present invention related generally to a low pass filter. More particularly, the invention relates to a low pass filter (hereinafter referred to as xe2x80x9cLPFxe2x80x9d) for infrared ray, in which a filter input is one bit, a tap coefficient of the LPF is one bit and a filter output is one bit.
2. Description of the Related Art
A typical construction of the conventional LPF has been disclosed in Japanese Unexamined Patent Publication No. Heisei 2-284513. The LPF disclosed in the above-identified publication is constructed with a Finite-duration Impulse-Response (FIR) filter 101 and an Infinite-duration Impulse-Response (IIR) filter 102, as shown in FIG. 8.
In the FIR filter 101, among respective outputs of tap delay circuits T0 to T2N+M+1, respective outputs of the tap delay circuit T0 to TN are added by an adder 103 and respective outputs of the tap delay circuits TN+M+1 to T2N+M+1 are added by an adder 104, respectively. Then, an adder output of the adder 104 is inverted by an inverter 105, and then is added to the adder output of the adder 103 by an adder 106. An adder output of the adder 106 is input to the IIR filter 102 to obtain a final output. It should be noted that D in FIG. 8 is a delay element.
In the meanwhile, since the LPF discussed about is adapted to multiple bit input, a circuit construction corresponding to the tap delay circuits T0 to TN in FIG. 8 and the adder 103 is required for adapting to one bit input. Therefore, the circuit shown in FIG. 8 is re-writtenas shown in FIG. 9. Namely, the LPF shown in FIG. 9 is the LPF to be used upon demodulation of a signal modulated by a particular frequency, typically an infrared signal. An input X(z) and an output H(z) of the LPF are one bit, respectively, and a multiplying coefficient is xe2x80x9c1xe2x80x9d. The LPF of FIG. 9 is constructed with a data input terminal 1 for inputting an input X(z) of a data string sampled at a sampling frequency f, tap delay circuits T1 to T6 connected to the data input terminal 1 in series for generating a tap delay information of an impulse response, an OR circuit G1 for superimposing tap delay information of the tap delay circuits T1 to T6, and a data output terminal 2 for outputting an output H(z) as a result of superimposing. A filter characteristics of such LPF is determined depending upon number of steps of the tap delay circuits T1 to T6.
Operation of the circuit construction shown in FIG. 9 will be discussed with reference to a timing chart of FIG. 10. For simplification of disclosure, number of stages of the tap delay circuits is set to three stages in FIG. 10. On the other hand, signals of the pulse response 1 to the pulse response 3 are prepared for the purpose of disclosure and represent impulse response as filters for respective pulses of the input X(z).
In FIG. 10, when a pulse P1 as the input X(z) is input in synchronism with a sampling clock, a pulse response 1 corresponding to a period during which the pulse P1 is input and a tap calculation period T for the pulse P1, is obtained. Since no pulse is present before and after the pulse P1, the pulse response 1 corresponding to the pulse P1 is fed in a form of solitary wave as a demodulated output H(z), as is.
Next, the pulse response 1 is similarly obtained for the pulse P2 input as X(z). In the shown case, next pulse P3 is input while responding to the pulse P2. The pulse response for the pulse P3 is executed at a timing of the pulse response 2. On the other hand, a pulse P4 is input while responding to the pulse P3. Similarly, pulse response is executed at a timing of the pulse response 3.
Here, the demodulated output H(z) for the pulse P2 to the pulse P4 is output with obtaining OR of respective pulse responses. At this time, the demodulated output H(z) becomes a signal in which xe2x80x9c0xe2x80x9d during a period from the pulse P2 to the pulse P3 are smoothed.
In the foregoing conventional LPF, the following drawback is encountered. At first, in the circuit construction shown in FIG. 9, greater number of stages of the tap delay circuits caused greater circuit scale. When the circuit scale is greater, it becomes impossible to equip in a portable equipment.
Next, in the circuit construction shown in FIG. 9, tap delay circuits corresponding to total tap number becomes necessary. As the tap delay circuit, ordinary flip-flop (F/F) is used, and F/Fs in number corresponding to the total tap number are connected in series. In this case, F/Fs in number corresponding to the tap number even when the input X(z) to the filter is not present, is consumed by power by the clock input. When the LPF is packed into LSI, power consumption inherently becomes large,
The present invention has been worked out for solving the drawbacks in the prior art. It is therefore an object of the present invention to provide an LPF for infrared ray which can realize reduction of circuit scale, lowering of power consumption and improvement of response to switching of number of taps.
According to the first aspect of the present invention, a low pass filter comprises:
counting means for initiating a counting operation in response to a data input and continuing the counting operation until as an externally designated total tap number is reached, for leading out a counted value as a filter output upon completion of the counting operation.
According to the second aspect of the present invention, a low pass filter comprises:
time measuring means for initiating a time measuring operation in response to a data input for leading out a counted value as a filter output upon completion of the time measuring operation.
In the first and second aspect of the present invention it is preferred that the counting means or the time measuring means comprises:
a first m-bit selection circuit, wherein m is a positive integer;
a second m-bit selection circuit taking an output of the first m-bit selection circuit and a first fixed value for selectively outputting the output of the first m-bit selection circuit and the first fixed value depending upon an input data to own filter;
a m-bit flip-flop taking an output of the second m-bit selection circuit as an input data;
a first comparator circuit comparing an output data of the m-bit flip-flop and a second fixed value;
a m-bit adder circuit for adding an output of the first comparator circuit to the least significant bit of the output data of the m-bit flip-flop; and
a second comparator circuit for comparing the output data of the m-bit flip-flop and an externally input total tap number value,
the first m-bit selection circuit taking an output of the m-bit adder and a third fixed value as inputs for selectively outputting one of the output of the m-bit adder and the third fixed value depending upon an output of the second m-bit comparator circuit for leading the output of the first m-bit comparator circuit as a filter output.
According to the third aspect of the present invention, a low pass filter comprises:
counting means for initiating a counting operation in response to a data input; and
comparing means for comparing a counted value counted by the counting means and an externally designated total tap number for leading out the counted value as a filter output when a result of comparison taken place by the comparing means shows matching of the counted value and the externally designated total tap number.
According to the fourth aspect of the present invention. a low pass filter comprising:
time measuring means for initiating a time measuring operation in response to a data input; and
comparing means for comparing a measured time measured by the time measuring means and an externally designated total tap number for leading out the counted value as a filter output when a result of comparison taken place by the comparing means shows matching of the measured time and the externally designated total tap number.
In the foregoing third and fourth aspect of the present invention, it is preferred that the counting means or the time measuring means comprises:
a first m-bit selection circuit, wherein m is a positive integer;
a second m-bit selection circuit taking an output of the first m-bit selection circuit and a first fixed value for selectively outputting the output of the first m-bit selection circuit and the first fixed value depending upon an input data to own filter;
a m-bit flip-flop taking an output of the second m-bit selection circuit as an input data;
a comparator circuit comparing an output data of the m-bit flip-flop and a second fixed value; and
a m-bit adder circuit for adding an output of the first comparator circuit to the least significant bit of the output data of the m-bit flip-flop;
the first m-bit selection circuit taking an output of the m-bit adder and a third fixed value as inputs for selectively outputting one of the output of the m-bit adder and the third fixed value depending upon an output of the comparator circuit,
the comparator circuit comparing the output data of the m-bit flip-flop and an externally input total tap number for leading the output of the comparator circuit as a filter output.
In short, the low pass filter according to the present invention has the tap position counting means for counting the tap position of impulse response generated by the most recent input from the data input terminal. By comparison of the result of counting and the total tap number of the filter, judgment is made whether impulse response to the most recent data input is completed or not. As the output of the low pass filter, xe2x80x9cHxe2x80x9d level is required within the impulse response period and xe2x80x9cLxe2x80x9d level is required otherwise. The output of the comparator circuit employed in the present invention, a value equivalent to the low pass filter can be obtained. Also, the tap position counting portion according to the present invention is constructed with the flip-flop in equal number as the input signal setting the total tap number. Therefore, power consumption during stand-by state and in operation can be minimized.